1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more particularly an electrically erasable and programmable read only memory (EEPROM) with an error check and correction circuit.
2. Description of the Related Art
An error check and correction circuit (ECC) is generally provided with a memory device to improve its reliability since it is capable of checking and correcting defective memory cell readings.
In a memory device which includes an ECC based on Hamming code correction, error correction for a one byte field (i.e., 8 bits per field of row addressable memory) memory array, is achieved by providing 4 parity bit cells for each one byte field of data to be stored in the memory array.
Consequently, the ECC circuit parity cell array will necessarily require 50% more memory area than the same memory device without ECC. Thus, in adding ECC capability to a memory device, chip size is compromised.
With Hamming codes, error correction can also be performed on many different bit field sizes. This entails using additional parity bits in the memory array. To determine the number of parity bits needed to correct an error in a given number of data bits, the following inequality must be satisfied: EQU 2.sup.k .gtoreq.m+k+1 (a)
where `m` is the given number of data bits, one of which is to be corrected, and `k` is the number of parity bits needed for single error correction.
By taking advantage of multiple byte field memory addressing/accessing (i.e., m=16 bits (2-byte field); m=32 (4-byte field), m=64 (8-byte field; etc.), the reduced number of additional parity bits necessary, significantly decreases with increasing number of multiple bytes.
For example, from equation (a) above, it should be clear that for a 2-byte field (m=16), 5 (=K) parity bit cells are necessary. Similarly, for an 8-byte field, 7 parity bits are necessary.
A memory device employing a multiple-byte field ECC is shown in Korean Patent Publication No. 90-4831, filed by Hitachi Co, Ltd. in 1990.
In a 4-byte field, for single-error correction to be performed properly, 6 bits of parity cell bits are necessary. Thus, the extra parity bits will occupy an additional 18.8% of memory area, (i.e., 6 bits/32 bits; the 32 bits corresponding to the 4-byte data field).
Although a bigger multiple-byte field will require fewer parity bit cells per field (i.e., an 8-byte field requires 7 parity bits in addition to the 64 initial data bits [=8 bytes]; and a 4-byte field requires 6 parity bits in addition to the 32 initial data bits [=4 bytes]; etc.), bigger multiple-byte fields present an inherent drawback.
Because the number of parity bits per field (k), as a percentage of the total number of initial data bits (m), decrease with increasing field size, overall correction efficiency is diminished.
This is because, while an ECC may be capable of correcting one of 12 bits in a single-byte per field memory arrangement (8 data bits+4 parity bits), a memory arrangement with single-error correction and 4 bytes per field requires a 6-bit parity field so that one of 38 bits (32 data bits 6 parity bits) can be corrected.
Generally, because data bits are stored in a data array, while parity bits are stored in a memory array, and because both data and parity arrays consist essentially of non-volatile ROM cells, error correction is provided regardless of whether random data was simultaneously stored therein.
When an EEPROM uses a multiple-byte per field ECC, multiple bytes are generally written simultaneously to correctly generate the necessary parity bit information. As a result, data bytes in a multiple-byte field cannot be stored randomly.
Korean Patent Application No. 91-18832, filed on Oct. 25, 1991 by the present inventor, discloses a scheme for generating parity data from random memory data which is input but temporarily stored until parity generation is completed, at which time both the memory data and the parity data is stored into respective array portions.
Such a conventional multiple-byte (4-byte) per field memory device with error checking and correction (ECC) capability is shown in FIG. 1. As shown, input data through data input buffer 280 is selected by input data selector 270, 1 byte at a time. Each byte is then loaded by first column decoder 160 into page buffer 110 in response to an input address.
After 128 address transitions, 128 bytes of random input data is loaded into respective page buffers (1 byte input data being received at each address transition).
When this input data, i.e., 128 bytes--corresponding to a page, is loaded into page buffer 110 of memory array 100, a parity generation period (Tpg) is initiated.
At this point, internal column generation circuit 170 automatically generates internal column address signals, one for each of 32 (4-byte) sets of data to be loaded as a single page in memory page buffer 110.
In response to this internal column address, first column decoder 160 is enabled causing page sense amplifier 500 to read out each set (4 bytes) of data through column gate 120.
Each set of memory data read out by page sense amplifier 500 is then fed to parity generator 200, where 6 parity bits corresponding to the 4-byte set (m=32 bits) are generated.
This 6-bit parity data is loaded into a parity page buffer in a parity cell array portion (not shown) of memory array 100.
The steps associated with reading out each data set stored in page buffer 110 of memory cell array 100 and generating parity data into a corresponding parity page buffer memory location (not shown), are repeated 32 times within parity generation period Tpg to provide parity generation for each of the 32 sets stored in page buffer 110.
Thus, all of the 32 sets (1k-bits) of input data, together with corresponding 6-bit parity data associated therewith, are temporarily stored into memory page buffer 110.
During program mode, input data and parity data stored in memory page buffer 110 are respectively copied, simultaneously therefrom, to memory array 100 in selected memory cells of a memory cell array (not shown) and in selected memory cells of a parity cell array (not shown).
During read mode, first column decoder 160 responds to a selected address causing sense amplifier 210 and parity sense amplifier 400 to respectively read out a memory data set (4 bytes=32 bits) and corresponding 6-bit parity data information.
The 6-bit parity data is input to parity generator 200 which is responsible for providing the correct 6-bit parity data associated with the selected memory data set.
The parity data is then delivered to error correction decoder 230. An output signal from error correction decoder 230 is compared with memory data using an exclusive OR-gate present in corrector 220. In turn, when any one arbitrary memory data bit is found to be in error, this bit is corrected by the read parity data.
Subsequently, an output from corrector 220 is decoded by sense amplifier decoder 240 controlled by output signals YS1-YS4 from second column decoder 290.
Sense amplifier decoder 240 output is then selected by data output buffer 250 to generate a one byte data.
In a conventional EEPROM having an ECC as described above, externally input data is transferred via bit lines to page buffer 110.
When these bit lines are defective, as may result under high leakage conditions, originally input data may be distorted when loaded into page buffer 110.
Even when no data error results from loading data into page buffer 110, because data temporarily stored in page buffer 110 is read out via separate bit lines in order to generate parity data, when either these same bit lines or when memory cells connected thereto have a defect, data transferred from page buffer 110 will likely be distorted and mistakenly fed as an input to parity generator 200.
Consequently, wrong parity data, having no true parity relation to the memory data, is produced--and the corrector 220 is unable to achieve precise error correction.
Drains and gates of memory cells used in EEPROM's have applied to them high voltages (about 20 V) which subject these cells to high stress. As a result, tunnel oxides between respective gates and drains (or alternatively, gate oxides between respective gates and drains) may be destroyed.
In addition, bit lines can cause current leakage resulting from weak junctions or from residual polysilicon particles remaining from the semiconductor manufacturing process.
Although these factors may not adversely affect ECC operation in EEPROMs which employ parity data as supplied externally from the EEPROM chip, these factors take on a significant role in on-chip ECC environments where parity data is provided immediately upon a reading out of memory data from memory cells therein.